Timing delay and reset circuit



Oct. 23, 1962 J. RYWAK TIMING DELAY AND RESET CIRCUIT Filed March 7, 1960 United States Patent 3,060,350 TIMING DELAY AND RESET CIRCUIT John Rywak, Belleville, Ontario, Canada, assignor to Northern Electric Company, Limited, Montreal, Quebec, Canada, a corporation of Canada Filed Mar. 7, 1960, Ser. No. 13,170 3 Claims. (Cl. 317-148.5)

This invention relates to timing circuits and more particularly to circuits for delaying the energizing of a current responsive device and the rapid reset of the device after the operation thereof.

It is frequently desirable to provide a timing interval between the operation and release of a current responsive device. This is conventionally accomplished by associating a resistor capacitor network with the control winding of the device. Inaccuracies in the timing of the operation and release of the device appear in the utilization of these prior circuits occurring from the fact that the point at which the energizing current must be reduced to permit the release of the electromagnetic element varies over a wide range on successive operations, and from the fact that with capacitors of a practical size, the slope of the voltage versus current curve for the release of the device is small.

It is an object of this invention to provide a timing circuit having a predetermined interval between the operation and release of a current responsive device in which the variations in the timing of the operation and release of a current responsive device is reduced.

It is another object of this invention to provide a timing circuit having the foregoing characteristics, having means by which the release of the current responsive device is accelerated.

A further object of this invention is to provide a time delay circuit having the foregoing characteristics in which the disengagement of the contacts of the current responsive device is accelerated.

:It is another object of this invention to provide a timing circuit having the foregoing characteristics in which the delay interval is eifective immediately after the release of the current responsive device.

These and other objects of this invention are attained in one embodiment of the invention by providing a resistor-capacitor timing network, in which is included the control winding of a current responsive device and a unidirectional element, poled so that the capacitor is charged when the circuit is energized, a transistor circuit connected across the capacitor and a voltage dividing circuit connected to the input of the transistor.

A better understanding of the invention may be attained by referring to the following drawings, in which:

FIG. 1 illustrates a circuit schematic in which the invention is represented, and

FIG. 2 illustrates a graph for the voltage-time discharge of the energy in the timing circuit during the release of the current responsive device.

Considering the drawings, there is shown a time delay network comprising adjustable resistor 1, capacitor 2, a current responsive device 3 having control coil 4 and contacts 4, unidirectional devices 5, 6.

Connected across the capacitor 2 is the transistor 7, collector resistor S and biasing resistors 9, 10. Also shown in this drawing is switch 11 and resistor 12.

3,060,350 Patented Oct. 23., 1962 ice Representative values of the elements employed in the circuit are as follows:

Resistor:

12 3.3K. 1 0 to 14K. Capacitor 2 50 mf. Coil 4 2.8K. (D.C' resistance).

Potentials derived when the representative resistance values are employed:

E +20v01ts.

Switch 11 Switch 11 Closed Open Initial Final, Initial, Final V- V.

1 Rises instantaneous from 0 to 19.6 volts.

In the operation of the circuit upon the closing of switch 11, unidirectional device 5 conducts so that capacitor 2 charges, unidirectional device 6 remaining nonconductive. With the representative resistance values listed heretofore, reference point 14 becomes positive with respect to reference point 13 simultaneously with the closing of switch 11. Transistor 7 is therefore cut 011 and diode 5 becomes conducting so that capacitor 2 charges. After a predetermined time interval, controlled by the adjustment of variable resistor 1, the potential of the reference point e rises to a value required for the operation of the current responsive device 3.

Upon the opening of switch 11, the potential of the reference point 14 falls below the potential of reference point 13 which allows transistor 7 to be forward biased so as to conduct. The action of the transistor 7 conducting allows the potential at reference point e to fall below the potential at reference point 13 so that diode 5 again becomes non-conducting.

When the switch 11 is suddenly opened, unidirectional device 6 arrests the negative voltage swing due to the inductance of control coil 4.

The voltage dividing network, comprised of resistors 9 and 10, which held transistor 7 non-conducting when switch 11 was closed, now allows the transistor to go into saturated conduction and through resistor 8 rapidly discharges capacitor 2. The purpose of resistor 8 is to limit the peak discharge current to a safe value for transistor 7.

What is claimed is:

1. A timing circuit adapted to delay the operation of a current responsive device after the application of a source of voltage through a controlling switch and to rapidly reset the device after the removal of such source voltage comprising in combination: a charging circuit consisting of a controlling switch, in series with a first resistor, a current responsive device having in parallel therewith a series combination of a resistor, a diode poled in the forward direction and a capacitor; a discharging circuit consisting of a transistor having a second resistor connected at one end to the base electrode of the transistor, a third resistor connected at one end to the collector electrode, the other end of such second and third resistors being connected to one terminal of the capacitor with the emitter electrode of the transistor connected to the other terminal of the capacitor; a transistor biasing resistor connected between the junction point of the switch and the first resistor and to the base electrode of the transistor.

2. A timing circuit in accordance with claim 1 in which the said circuit responsive device consists of a control winding with a unidirectional element connected across the control winding poled to be non-conducting when an energizing pulse is applied to the energizing circuit.

3. A timing circuit in accordance with claim 2 having in combination in the timing circuit an adjustable resistor.

References Cited in the file of this patent UNITED STATES PATENTS OTHER REFERENCES Core Driver (W. L. Stahl and W. R. Vincent), IBM Technical Disclosure Bulletin, page 26, volume 2, No. 1,

15 June 1959. 

